The present invention relates to a fabrication process of a heterojunction bipolar transistor and more particularly to a process for fabrication a heterojunction bipolar transistor suitable for forming a planar structure.
A heterojunction bipolar transistor (HBT) wherein a compound semiconductor is used attracts attention as a next generation high speed device. FIG. 1 is a schematic cross-sectional view of a conventional mesa-type HBT. In general, the above-described device is fabricated as follows. An n.sup.+ -type GaAs subcollector layer 22, an n-type GaAs collector layer 23, a p.sup.+ -type GaAs base layer 24, an n-type AlGaAs emitter layer 25, and an n.sup.+ -type GaAs cap layer 26 are successively formed on a semiinsulating GaAs substrate 21 by the MBE method or the like, and the surface of each of the base layer 24 and the subcollector layer 22 is exposed by mesa etching to form electrodes 27, 28 and 29 respectively corresponding to an emitter, a base, and a collector, thereby completing the device.
The mesa-type HBT thus prepared, however, had a problem that the breaking of the wire due to the presence of unevennesses of the device makes the integration for the purpose of taking advantage of excellent current-driving force impossible. In order to eliminate this drawback, studies have been made on the fabrication of a device with a planar structure. The fabrication of such a device makes it necessary to draw out the base or collector electrode on the surface of the substrate. Ion implantation technique has been used for the formation of a conductive layer for this purpose. However, it is very difficult to convert a deep region ranging from the surface of the n-type AlGaAs emitter layer 25 to the n.sup.+ -type GaAs subcollector layer 22 including the p.sup.+ base layer 24 located therebetween into a highly doped n.sup.+ -type through ion implantation of n-type impurities. Even if it is possible to achieve this conversion, annealing at a high temperature after the ion implantation unfavorably exerts an adverse effect on the characteristics of the heterojunction interface formed by epitaxial growth.
A method of drawing out a collector electrode on the surface of the device without using the ion implantation technique is described in, e.g., Technical Report ED84-67 of the Institute of Electronics and Communication Engineers of Japan, pp. 39.about.46. In this method, a contact hole which reaches the n.sup.+ -type GaAs subcollector layer is formed by etching and a metal is then buried in this hole by the lift-off method to flatten the surface.